🤖 LLM Hardware Verification
Generate hardware designs and verification tests using AI
1 Hardware
→
2 BDD Tests
→
3 Testbench
→
4 Simulation
Hardware → Tests: Write hardware first, then generate tests to verify it
Current
1
🔧 Hardware Design (DUV)
Generate with LLM or upload existing Verilog file
Pending
▼
⚡ Configuration
or use natural language
Examples:
16-bit ALU
32-bit Counter
32x32 RegFile
RISC-V CPU
⚡ Stream output
Generating...
✅
Generating...
Ready to generate
LLM
Verilog Code Preview
🔬
Yosys Synthesis Analysis
▼
Running Yosys synthesis...
Drag & drop your Verilog file here
or click to browse
📄 .v, .sv files
📏 Max 1MB
🔒 Secure upload
alu_16bit.v
2.3 KB • Uploaded successfully
Module Name
alu_16bit
Detected Type
ALU
High
Bitwidth
16-bit
Inputs
clk, rst_n, A, B, opcode
Outputs
result, zero, overflow
🔧 Adjust Detection (Optional)
🔬
Yosys Synthesis Analysis
▼
Running Yosys synthesis...
2
🧪 BDD Specification Scenarios
Generate with LLM or upload existing .feature file
Pending
▼
Current DUT
- • - • -
-
LLM
No Hardware Generated
Complete Step 1 first to generate or upload hardware.
⚡ Configuration
Examples:
Basic test
Boundary
Reset
⚡ Stream output
Generating...
✅
Generating...
Ready to generate
LLM
BDD Feature Preview
Drag & drop your BDD feature file here
or click to browse
📄 .feature files
📏 Max 1MB
🔒 Secure upload
test.feature
2.3 KB • Uploaded successfully
Feature Name
-
Scenarios
0
📋 File Preview
3
⚙️ Verilog Testbench
Generate from BDD or upload existing testbench
Pending
▼
Source BDD
- • -
-
No BDD File Generated
Complete Step 2 first to generate BDD test scenarios.
⚡ Configuration
✅
Generating...
Ready to generate
TB
Quality Score
-
-
Test Cases
-
Operations Covered
-
Corner Cases
-
Testbench Preview
✅
Batch Generation Complete
-
BATCH
Total Testbenches
-
LLM Providers
-
Results by LLM
Drag & drop your Verilog testbench file here
or click to browse
📄 .v, .sv files
📏 Max 1MB
🔒 Secure upload
testbench.v
4.5 KB • Uploaded successfully
Module Name
-
Test Count (estimated)
0
📋 File Preview
4
🚀 Run Simulation
Execute testbench and view results
Pending
▼
Simulation Tools
Checking...
...
No Testbench Available
Complete Step 3 first to generate a testbench.
⚡ Configuration
Testbench
-
DUT
-
✅
Simulation Complete
-
SIM
Total Tests
-
Passed
-
Failed
-
Pass Rate
-
-
Compile Time
-
Simulation Time
-
📋 Simulation Log
✅
Batch Simulation Complete
-
BATCH
Total Simulations
-
Successful
-
Overall Pass Rate
-
Results by LLM